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OCR A Level CPU Simulator

8 bit binary Von Neumann CPU simulator extending Little Man Computer to show registers and busses required by OCR A Level

Pete Dring

Created by Pete Dring
last edited Sep 25 2017 by Pete Dring


The OCR A Level spec states that students should be able to explain:

  • The Arithmetic and Logic Unit; ALU, Control Unit and Registers (Program Counter; PC, Accumulator; ACC, Memory Address Register; MAR, Memory Data Register; MDR, Current Instruction Register; CIR).

  • Buses: data, address and control: how this relates to assembly language programs.

  • The Fetch-Decode-Execute Cycle; including its effects on registers.

There’s a range of Little Man Computer CPU simulators out there (see linked resources) including Peter Higginson’s excellent tool that illustrate the fetch-decode-execute cycle but there are some limitations to the LMC model which means the LMC model needs supplementing with additional information at A level:

  • LMC uses denary numbers rather than binary for its instructions and data.

  • LMC doesn’t have MDR or MAR registers and it’s not always clear what values are sent on each bus.

This resource is an attempt to adapt the LMC model to an 8 bit binary CPU with just the features specified by the OCR A level.

It’s designed to follow on from the excellent Craig’n’Dave video about the fetch decode execute cycle.

You can try out the simulator here or download the source here.

I hope it’s useful.

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